
point-yz:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004004c0 <_init>:
  4004c0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4004c4:	910003fd 	mov	x29, sp
  4004c8:	94000034 	bl	400598 <call_weak_fn>
  4004cc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4004d0:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004e0 <.plt>:
  4004e0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004e4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xf47c>
  4004e8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ec:	913fe210 	add	x16, x16, #0xff8
  4004f0:	d61f0220 	br	x17
  4004f4:	d503201f 	nop
  4004f8:	d503201f 	nop
  4004fc:	d503201f 	nop

0000000000400500 <__libc_start_main@plt>:
  400500:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400504:	f9400211 	ldr	x17, [x16]
  400508:	91000210 	add	x16, x16, #0x0
  40050c:	d61f0220 	br	x17

0000000000400510 <__gmon_start__@plt>:
  400510:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400514:	f9400611 	ldr	x17, [x16, #8]
  400518:	91002210 	add	x16, x16, #0x8
  40051c:	d61f0220 	br	x17

0000000000400520 <abort@plt>:
  400520:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400524:	f9400a11 	ldr	x17, [x16, #16]
  400528:	91004210 	add	x16, x16, #0x10
  40052c:	d61f0220 	br	x17

0000000000400530 <puts@plt>:
  400530:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400534:	f9400e11 	ldr	x17, [x16, #24]
  400538:	91006210 	add	x16, x16, #0x18
  40053c:	d61f0220 	br	x17

0000000000400540 <printf@plt>:
  400540:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400544:	f9401211 	ldr	x17, [x16, #32]
  400548:	91008210 	add	x16, x16, #0x20
  40054c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400550 <_start>:
  400550:	d280001d 	mov	x29, #0x0                   	// #0
  400554:	d280001e 	mov	x30, #0x0                   	// #0
  400558:	aa0003e5 	mov	x5, x0
  40055c:	f94003e1 	ldr	x1, [sp]
  400560:	910023e2 	add	x2, sp, #0x8
  400564:	910003e6 	mov	x6, sp
  400568:	580000c0 	ldr	x0, 400580 <_start+0x30>
  40056c:	580000e3 	ldr	x3, 400588 <_start+0x38>
  400570:	58000104 	ldr	x4, 400590 <_start+0x40>
  400574:	97ffffe3 	bl	400500 <__libc_start_main@plt>
  400578:	97ffffea 	bl	400520 <abort@plt>
  40057c:	00000000 	.inst	0x00000000 ; undefined
  400580:	00401578 	.word	0x00401578
  400584:	00000000 	.word	0x00000000
  400588:	00401580 	.word	0x00401580
  40058c:	00000000 	.word	0x00000000
  400590:	00401600 	.word	0x00401600
  400594:	00000000 	.word	0x00000000

0000000000400598 <call_weak_fn>:
  400598:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xf47c>
  40059c:	f947f000 	ldr	x0, [x0, #4064]
  4005a0:	b4000040 	cbz	x0, 4005a8 <call_weak_fn+0x10>
  4005a4:	17ffffdb 	b	400510 <__gmon_start__@plt>
  4005a8:	d65f03c0 	ret
  4005ac:	00000000 	.inst	0x00000000 ; undefined

00000000004005b0 <deregister_tm_clones>:
  4005b0:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4005b4:	9100e000 	add	x0, x0, #0x38
  4005b8:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  4005bc:	9100e021 	add	x1, x1, #0x38
  4005c0:	eb00003f 	cmp	x1, x0
  4005c4:	540000a0 	b.eq	4005d8 <deregister_tm_clones+0x28>  // b.none
  4005c8:	b0000001 	adrp	x1, 401000 <ggg+0x438>
  4005cc:	f9431021 	ldr	x1, [x1, #1568]
  4005d0:	b4000041 	cbz	x1, 4005d8 <deregister_tm_clones+0x28>
  4005d4:	d61f0020 	br	x1
  4005d8:	d65f03c0 	ret
  4005dc:	d503201f 	nop

00000000004005e0 <register_tm_clones>:
  4005e0:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4005e4:	9100e000 	add	x0, x0, #0x38
  4005e8:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  4005ec:	9100e021 	add	x1, x1, #0x38
  4005f0:	cb000021 	sub	x1, x1, x0
  4005f4:	9343fc21 	asr	x1, x1, #3
  4005f8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005fc:	9341fc21 	asr	x1, x1, #1
  400600:	b40000a1 	cbz	x1, 400614 <register_tm_clones+0x34>
  400604:	b0000002 	adrp	x2, 401000 <ggg+0x438>
  400608:	f9431442 	ldr	x2, [x2, #1576]
  40060c:	b4000042 	cbz	x2, 400614 <register_tm_clones+0x34>
  400610:	d61f0040 	br	x2
  400614:	d65f03c0 	ret

0000000000400618 <__do_global_dtors_aux>:
  400618:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40061c:	910003fd 	mov	x29, sp
  400620:	f9000bf3 	str	x19, [sp, #16]
  400624:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  400628:	3940e260 	ldrb	w0, [x19, #56]
  40062c:	35000080 	cbnz	w0, 40063c <__do_global_dtors_aux+0x24>
  400630:	97ffffe0 	bl	4005b0 <deregister_tm_clones>
  400634:	52800020 	mov	w0, #0x1                   	// #1
  400638:	3900e260 	strb	w0, [x19, #56]
  40063c:	f9400bf3 	ldr	x19, [sp, #16]
  400640:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400644:	d65f03c0 	ret

0000000000400648 <frame_dummy>:
  400648:	17ffffe6 	b	4005e0 <register_tm_clones>

000000000040064c <aaa>:
  40064c:	d503201f 	nop
  400650:	d65f03c0 	ret

0000000000400654 <bbb>:
  400654:	d10043ff 	sub	sp, sp, #0x10
  400658:	52800080 	mov	w0, #0x4                   	// #4
  40065c:	b90007e0 	str	w0, [sp, #4]
  400660:	910013e0 	add	x0, sp, #0x4
  400664:	f90007e0 	str	x0, [sp, #8]
  400668:	d503201f 	nop
  40066c:	910043ff 	add	sp, sp, #0x10
  400670:	d65f03c0 	ret

0000000000400674 <ccc>:
  400674:	d100c3ff 	sub	sp, sp, #0x30
  400678:	910003e0 	mov	x0, sp
  40067c:	f90017e0 	str	x0, [sp, #40]
  400680:	910003e0 	mov	x0, sp
  400684:	f90017e0 	str	x0, [sp, #40]
  400688:	d503201f 	nop
  40068c:	9100c3ff 	add	sp, sp, #0x30
  400690:	d65f03c0 	ret

0000000000400694 <ddd>:
  400694:	d100c3ff 	sub	sp, sp, #0x30
  400698:	52800020 	mov	w0, #0x1                   	// #1
  40069c:	b90003e0 	str	w0, [sp]
  4006a0:	52800040 	mov	w0, #0x2                   	// #2
  4006a4:	b90007e0 	str	w0, [sp, #4]
  4006a8:	52800060 	mov	w0, #0x3                   	// #3
  4006ac:	b9000be0 	str	w0, [sp, #8]
  4006b0:	910003e0 	mov	x0, sp
  4006b4:	f90017e0 	str	x0, [sp, #40]
  4006b8:	910003e0 	mov	x0, sp
  4006bc:	f90017e0 	str	x0, [sp, #40]
  4006c0:	d503201f 	nop
  4006c4:	9100c3ff 	add	sp, sp, #0x30
  4006c8:	d65f03c0 	ret

00000000004006cc <eee>:
  4006cc:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  4006d0:	910003fd 	mov	x29, sp
  4006d4:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  4006d8:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  4006dc:	f9001fbf 	str	xzr, [x29, #56]
  4006e0:	52800140 	mov	w0, #0xa                   	// #10
  4006e4:	b9001ba0 	str	w0, [x29, #24]
  4006e8:	528001e0 	mov	w0, #0xf                   	// #15
  4006ec:	b9001fa0 	str	w0, [x29, #28]
  4006f0:	52800280 	mov	w0, #0x14                  	// #20
  4006f4:	b90023a0 	str	w0, [x29, #32]
  4006f8:	52800320 	mov	w0, #0x19                  	// #25
  4006fc:	b90027a0 	str	w0, [x29, #36]
  400700:	528003c0 	mov	w0, #0x1e                  	// #30
  400704:	b9002ba0 	str	w0, [x29, #40]
  400708:	52800460 	mov	w0, #0x23                  	// #35
  40070c:	b9002fa0 	str	w0, [x29, #44]
  400710:	52800500 	mov	w0, #0x28                  	// #40
  400714:	b90033a0 	str	w0, [x29, #48]
  400718:	910063a0 	add	x0, x29, #0x18
  40071c:	f90027a0 	str	x0, [x29, #72]
  400720:	f94027a0 	ldr	x0, [x29, #72]
  400724:	91003000 	add	x0, x0, #0xc
  400728:	f90027a0 	str	x0, [x29, #72]
  40072c:	f94027a0 	ldr	x0, [x29, #72]
  400730:	b9400001 	ldr	w1, [x0]
  400734:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400738:	9118c000 	add	x0, x0, #0x630
  40073c:	97ffff81 	bl	400540 <printf@plt>
  400740:	f94027a0 	ldr	x0, [x29, #72]
  400744:	91003000 	add	x0, x0, #0xc
  400748:	b9400001 	ldr	w1, [x0]
  40074c:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400750:	9118c000 	add	x0, x0, #0x630
  400754:	97ffff7b 	bl	400540 <printf@plt>
  400758:	f94027a0 	ldr	x0, [x29, #72]
  40075c:	91003000 	add	x0, x0, #0xc
  400760:	b9400001 	ldr	w1, [x0]
  400764:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400768:	9118c000 	add	x0, x0, #0x630
  40076c:	97ffff75 	bl	400540 <printf@plt>
  400770:	910063a0 	add	x0, x29, #0x18
  400774:	f90027a0 	str	x0, [x29, #72]
  400778:	f94027a0 	ldr	x0, [x29, #72]
  40077c:	91003000 	add	x0, x0, #0xc
  400780:	b9400001 	ldr	w1, [x0]
  400784:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400788:	9118c000 	add	x0, x0, #0x630
  40078c:	97ffff6d 	bl	400540 <printf@plt>
  400790:	f94027a0 	ldr	x0, [x29, #72]
  400794:	91003000 	add	x0, x0, #0xc
  400798:	b9400001 	ldr	w1, [x0]
  40079c:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4007a0:	9118c000 	add	x0, x0, #0x630
  4007a4:	97ffff67 	bl	400540 <printf@plt>
  4007a8:	f94027a0 	ldr	x0, [x29, #72]
  4007ac:	91001000 	add	x0, x0, #0x4
  4007b0:	f90027a0 	str	x0, [x29, #72]
  4007b4:	f94027a0 	ldr	x0, [x29, #72]
  4007b8:	b9400001 	ldr	w1, [x0]
  4007bc:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4007c0:	9118c000 	add	x0, x0, #0x630
  4007c4:	97ffff5f 	bl	400540 <printf@plt>
  4007c8:	910063a0 	add	x0, x29, #0x18
  4007cc:	f90027a0 	str	x0, [x29, #72]
  4007d0:	f94027a0 	ldr	x0, [x29, #72]
  4007d4:	f90023a0 	str	x0, [x29, #64]
  4007d8:	f94023a0 	ldr	x0, [x29, #64]
  4007dc:	b9400001 	ldr	w1, [x0]
  4007e0:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4007e4:	9118e000 	add	x0, x0, #0x638
  4007e8:	2a0103e2 	mov	w2, w1
  4007ec:	528007c1 	mov	w1, #0x3e                  	// #62
  4007f0:	97ffff54 	bl	400540 <printf@plt>
  4007f4:	f94023a0 	ldr	x0, [x29, #64]
  4007f8:	91001000 	add	x0, x0, #0x4
  4007fc:	f90023a0 	str	x0, [x29, #64]
  400800:	f94023a0 	ldr	x0, [x29, #64]
  400804:	b9400001 	ldr	w1, [x0]
  400808:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  40080c:	9118e000 	add	x0, x0, #0x638
  400810:	2a0103e2 	mov	w2, w1
  400814:	52800801 	mov	w1, #0x40                  	// #64
  400818:	97ffff4a 	bl	400540 <printf@plt>
  40081c:	f94023a0 	ldr	x0, [x29, #64]
  400820:	91001000 	add	x0, x0, #0x4
  400824:	f90023a0 	str	x0, [x29, #64]
  400828:	f94023a0 	ldr	x0, [x29, #64]
  40082c:	b9400001 	ldr	w1, [x0]
  400830:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400834:	9118e000 	add	x0, x0, #0x638
  400838:	2a0103e2 	mov	w2, w1
  40083c:	52800821 	mov	w1, #0x41                  	// #65
  400840:	97ffff40 	bl	400540 <printf@plt>
  400844:	f94027a0 	ldr	x0, [x29, #72]
  400848:	b9400001 	ldr	w1, [x0]
  40084c:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400850:	91192000 	add	x0, x0, #0x648
  400854:	2a0103e2 	mov	w2, w1
  400858:	52800841 	mov	w1, #0x42                  	// #66
  40085c:	97ffff39 	bl	400540 <printf@plt>
  400860:	d503201f 	nop
  400864:	a8c57bfd 	ldp	x29, x30, [sp], #80
  400868:	d65f03c0 	ret

000000000040086c <fff>:
  40086c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400870:	910003fd 	mov	x29, sp
  400874:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400878:	91212000 	add	x0, x0, #0x848
  40087c:	910083a2 	add	x2, x29, #0x20
  400880:	aa0003e3 	mov	x3, x0
  400884:	a9400460 	ldp	x0, x1, [x3]
  400888:	a9000440 	stp	x0, x1, [x2]
  40088c:	b9401060 	ldr	w0, [x3, #16]
  400890:	b9001040 	str	w0, [x2, #16]
  400894:	910083a0 	add	x0, x29, #0x20
  400898:	f9000fa0 	str	x0, [x29, #24]
  40089c:	910083a0 	add	x0, x29, #0x20
  4008a0:	91002000 	add	x0, x0, #0x8
  4008a4:	f9000ba0 	str	x0, [x29, #16]
  4008a8:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4008ac:	91196000 	add	x0, x0, #0x658
  4008b0:	97ffff20 	bl	400530 <puts@plt>
  4008b4:	f9400fa1 	ldr	x1, [x29, #24]
  4008b8:	f9400fa0 	ldr	x0, [x29, #24]
  4008bc:	b9400002 	ldr	w2, [x0]
  4008c0:	910063a3 	add	x3, x29, #0x18
  4008c4:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4008c8:	911a4000 	add	x0, x0, #0x690
  4008cc:	97ffff1d 	bl	400540 <printf@plt>
  4008d0:	f9400fa0 	ldr	x0, [x29, #24]
  4008d4:	91004000 	add	x0, x0, #0x10
  4008d8:	f9001fa0 	str	x0, [x29, #56]
  4008dc:	f9401fa0 	ldr	x0, [x29, #56]
  4008e0:	b9400001 	ldr	w1, [x0]
  4008e4:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4008e8:	911ae000 	add	x0, x0, #0x6b8
  4008ec:	97ffff15 	bl	400540 <printf@plt>
  4008f0:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4008f4:	911b4000 	add	x0, x0, #0x6d0
  4008f8:	97ffff0e 	bl	400530 <puts@plt>
  4008fc:	f9400fa0 	ldr	x0, [x29, #24]
  400900:	91004001 	add	x1, x0, #0x10
  400904:	f9400fa0 	ldr	x0, [x29, #24]
  400908:	91003000 	add	x0, x0, #0xc
  40090c:	b9400002 	ldr	w2, [x0]
  400910:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400914:	911bc000 	add	x0, x0, #0x6f0
  400918:	97ffff0a 	bl	400540 <printf@plt>
  40091c:	f9400fa0 	ldr	x0, [x29, #24]
  400920:	91001000 	add	x0, x0, #0x4
  400924:	f9000fa0 	str	x0, [x29, #24]
  400928:	f9400fa0 	ldr	x0, [x29, #24]
  40092c:	b9400001 	ldr	w1, [x0]
  400930:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400934:	911ae000 	add	x0, x0, #0x6b8
  400938:	97ffff02 	bl	400540 <printf@plt>
  40093c:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400940:	911c6000 	add	x0, x0, #0x718
  400944:	97fffefb 	bl	400530 <puts@plt>
  400948:	f9400fa1 	ldr	x1, [x29, #24]
  40094c:	f9400fa0 	ldr	x0, [x29, #24]
  400950:	b9400002 	ldr	w2, [x0]
  400954:	910063a3 	add	x3, x29, #0x18
  400958:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  40095c:	911a4000 	add	x0, x0, #0x690
  400960:	97fffef8 	bl	400540 <printf@plt>
  400964:	f9400ba0 	ldr	x0, [x29, #16]
  400968:	d1001000 	sub	x0, x0, #0x4
  40096c:	f9000ba0 	str	x0, [x29, #16]
  400970:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400974:	911cc000 	add	x0, x0, #0x730
  400978:	97fffeee 	bl	400530 <puts@plt>
  40097c:	f9400ba1 	ldr	x1, [x29, #16]
  400980:	f9400ba0 	ldr	x0, [x29, #16]
  400984:	b9400002 	ldr	w2, [x0]
  400988:	910043a3 	add	x3, x29, #0x10
  40098c:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400990:	911d2000 	add	x0, x0, #0x748
  400994:	97fffeeb 	bl	400540 <printf@plt>
  400998:	f9400fa0 	ldr	x0, [x29, #24]
  40099c:	d1001000 	sub	x0, x0, #0x4
  4009a0:	f9000fa0 	str	x0, [x29, #24]
  4009a4:	f9400ba0 	ldr	x0, [x29, #16]
  4009a8:	91001000 	add	x0, x0, #0x4
  4009ac:	f9000ba0 	str	x0, [x29, #16]
  4009b0:	f9400fa0 	ldr	x0, [x29, #24]
  4009b4:	b9400001 	ldr	w1, [x0]
  4009b8:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4009bc:	911ae000 	add	x0, x0, #0x6b8
  4009c0:	97fffee0 	bl	400540 <printf@plt>
  4009c4:	f9400ba0 	ldr	x0, [x29, #16]
  4009c8:	b9400001 	ldr	w1, [x0]
  4009cc:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4009d0:	911ae000 	add	x0, x0, #0x6b8
  4009d4:	97fffedb 	bl	400540 <printf@plt>
  4009d8:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4009dc:	911dc000 	add	x0, x0, #0x770
  4009e0:	97fffed4 	bl	400530 <puts@plt>
  4009e4:	f9400fa1 	ldr	x1, [x29, #24]
  4009e8:	f9400ba2 	ldr	x2, [x29, #16]
  4009ec:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4009f0:	911e6000 	add	x0, x0, #0x798
  4009f4:	97fffed3 	bl	400540 <printf@plt>
  4009f8:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  4009fc:	911ec000 	add	x0, x0, #0x7b0
  400a00:	97fffecc 	bl	400530 <puts@plt>
  400a04:	f9400ba1 	ldr	x1, [x29, #16]
  400a08:	f9400fa2 	ldr	x2, [x29, #24]
  400a0c:	f9400ba0 	ldr	x0, [x29, #16]
  400a10:	aa0003e3 	mov	x3, x0
  400a14:	f9400fa0 	ldr	x0, [x29, #24]
  400a18:	cb000060 	sub	x0, x3, x0
  400a1c:	9342fc00 	asr	x0, x0, #2
  400a20:	aa0003e3 	mov	x3, x0
  400a24:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400a28:	911f6000 	add	x0, x0, #0x7d8
  400a2c:	97fffec5 	bl	400540 <printf@plt>
  400a30:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400a34:	91200000 	add	x0, x0, #0x800
  400a38:	97fffebe 	bl	400530 <puts@plt>
  400a3c:	f9401fa0 	ldr	x0, [x29, #56]
  400a40:	d1002001 	sub	x1, x0, #0x8
  400a44:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400a48:	9120a000 	add	x0, x0, #0x828
  400a4c:	aa0103e2 	mov	x2, x1
  400a50:	f9401fa1 	ldr	x1, [x29, #56]
  400a54:	97fffebb 	bl	400540 <printf@plt>
  400a58:	d503201f 	nop
  400a5c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400a60:	d65f03c0 	ret

0000000000400a64 <point>:
  400a64:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400a68:	910003fd 	mov	x29, sp
  400a6c:	52800c80 	mov	w0, #0x64                  	// #100
  400a70:	b90023a0 	str	w0, [x29, #32]
  400a74:	52801900 	mov	w0, #0xc8                  	// #200
  400a78:	b90027a0 	str	w0, [x29, #36]
  400a7c:	52802580 	mov	w0, #0x12c                 	// #300
  400a80:	b9001ba0 	str	w0, [x29, #24]
  400a84:	52803200 	mov	w0, #0x190                 	// #400
  400a88:	b9001fa0 	str	w0, [x29, #28]
  400a8c:	910083a0 	add	x0, x29, #0x20
  400a90:	f9001fa0 	str	x0, [x29, #56]
  400a94:	f9401fa0 	ldr	x0, [x29, #56]
  400a98:	f9001ba0 	str	x0, [x29, #48]
  400a9c:	910063a0 	add	x0, x29, #0x18
  400aa0:	f90017a0 	str	x0, [x29, #40]
  400aa4:	f9401ba0 	ldr	x0, [x29, #48]
  400aa8:	b9400001 	ldr	w1, [x0]
  400aac:	f9401fa0 	ldr	x0, [x29, #56]
  400ab0:	b9400002 	ldr	w2, [x0]
  400ab4:	f94017a0 	ldr	x0, [x29, #40]
  400ab8:	b9400003 	ldr	w3, [x0]
  400abc:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400ac0:	91218000 	add	x0, x0, #0x860
  400ac4:	97fffe9f 	bl	400540 <printf@plt>
  400ac8:	f9401ba0 	ldr	x0, [x29, #48]
  400acc:	91001001 	add	x1, x0, #0x4
  400ad0:	f9001ba1 	str	x1, [x29, #48]
  400ad4:	b9400005 	ldr	w5, [x0]
  400ad8:	f9401fa0 	ldr	x0, [x29, #56]
  400adc:	91001000 	add	x0, x0, #0x4
  400ae0:	f9001fa0 	str	x0, [x29, #56]
  400ae4:	f9401fa0 	ldr	x0, [x29, #56]
  400ae8:	b9400006 	ldr	w6, [x0]
  400aec:	f94017a0 	ldr	x0, [x29, #40]
  400af0:	b9400000 	ldr	w0, [x0]
  400af4:	11000402 	add	w2, w0, #0x1
  400af8:	f94017a1 	ldr	x1, [x29, #40]
  400afc:	b9000022 	str	w2, [x1]
  400b00:	b0000001 	adrp	x1, 401000 <ggg+0x438>
  400b04:	91222024 	add	x4, x1, #0x888
  400b08:	2a0003e3 	mov	w3, w0
  400b0c:	2a0603e2 	mov	w2, w6
  400b10:	2a0503e1 	mov	w1, w5
  400b14:	aa0403e0 	mov	x0, x4
  400b18:	97fffe8a 	bl	400540 <printf@plt>
  400b1c:	f9401ba0 	ldr	x0, [x29, #48]
  400b20:	b9400001 	ldr	w1, [x0]
  400b24:	f9401fa0 	ldr	x0, [x29, #56]
  400b28:	b9400002 	ldr	w2, [x0]
  400b2c:	f94017a0 	ldr	x0, [x29, #40]
  400b30:	b9400003 	ldr	w3, [x0]
  400b34:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400b38:	91218000 	add	x0, x0, #0x860
  400b3c:	97fffe81 	bl	400540 <printf@plt>
  400b40:	d503201f 	nop
  400b44:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400b48:	d65f03c0 	ret

0000000000400b4c <modify_array>:
  400b4c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400b50:	910003fd 	mov	x29, sp
  400b54:	52800c80 	mov	w0, #0x64                  	// #100
  400b58:	b9001ba0 	str	w0, [x29, #24]
  400b5c:	52801900 	mov	w0, #0xc8                  	// #200
  400b60:	b9001fa0 	str	w0, [x29, #28]
  400b64:	910063a0 	add	x0, x29, #0x18
  400b68:	f90013a0 	str	x0, [x29, #32]
  400b6c:	f94013a0 	ldr	x0, [x29, #32]
  400b70:	52800cc1 	mov	w1, #0x66                  	// #102
  400b74:	b9000001 	str	w1, [x0]
  400b78:	b9002fbf 	str	wzr, [x29, #44]
  400b7c:	1400000d 	b	400bb0 <modify_array+0x64>
  400b80:	b9802fa0 	ldrsw	x0, [x29, #44]
  400b84:	d37ef400 	lsl	x0, x0, #2
  400b88:	910063a1 	add	x1, x29, #0x18
  400b8c:	b8606821 	ldr	w1, [x1, x0]
  400b90:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400b94:	9122e000 	add	x0, x0, #0x8b8
  400b98:	2a0103e2 	mov	w2, w1
  400b9c:	b9402fa1 	ldr	w1, [x29, #44]
  400ba0:	97fffe68 	bl	400540 <printf@plt>
  400ba4:	b9402fa0 	ldr	w0, [x29, #44]
  400ba8:	11000400 	add	w0, w0, #0x1
  400bac:	b9002fa0 	str	w0, [x29, #44]
  400bb0:	b9402fa0 	ldr	w0, [x29, #44]
  400bb4:	7100041f 	cmp	w0, #0x1
  400bb8:	54fffe4d 	b.le	400b80 <modify_array+0x34>
  400bbc:	d503201f 	nop
  400bc0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400bc4:	d65f03c0 	ret

0000000000400bc8 <ggg>:
  400bc8:	a9aa7bfd 	stp	x29, x30, [sp, #-352]!
  400bcc:	910003fd 	mov	x29, sp
  400bd0:	a9137fbf 	stp	xzr, xzr, [x29, #304]
  400bd4:	a9147fbf 	stp	xzr, xzr, [x29, #320]
  400bd8:	f900abbf 	str	xzr, [x29, #336]
  400bdc:	52800140 	mov	w0, #0xa                   	// #10
  400be0:	b90133a0 	str	w0, [x29, #304]
  400be4:	528001e0 	mov	w0, #0xf                   	// #15
  400be8:	b90137a0 	str	w0, [x29, #308]
  400bec:	52800280 	mov	w0, #0x14                  	// #20
  400bf0:	b9013ba0 	str	w0, [x29, #312]
  400bf4:	52800320 	mov	w0, #0x19                  	// #25
  400bf8:	b9013fa0 	str	w0, [x29, #316]
  400bfc:	528003c0 	mov	w0, #0x1e                  	// #30
  400c00:	b90143a0 	str	w0, [x29, #320]
  400c04:	52800500 	mov	w0, #0x28                  	// #40
  400c08:	b90147a0 	str	w0, [x29, #324]
  400c0c:	910803a0 	add	x0, x29, #0x200
  400c10:	a930fc1f 	stp	xzr, xzr, [x0, #-248]
  400c14:	910803a0 	add	x0, x29, #0x200
  400c18:	a931fc1f 	stp	xzr, xzr, [x0, #-232]
  400c1c:	f90097bf 	str	xzr, [x29, #296]
  400c20:	52800140 	mov	w0, #0xa                   	// #10
  400c24:	b9010ba0 	str	w0, [x29, #264]
  400c28:	528001e0 	mov	w0, #0xf                   	// #15
  400c2c:	b9010fa0 	str	w0, [x29, #268]
  400c30:	52800280 	mov	w0, #0x14                  	// #20
  400c34:	b90113a0 	str	w0, [x29, #272]
  400c38:	52800320 	mov	w0, #0x19                  	// #25
  400c3c:	b90117a0 	str	w0, [x29, #276]
  400c40:	528003c0 	mov	w0, #0x1e                  	// #30
  400c44:	b9011ba0 	str	w0, [x29, #280]
  400c48:	52800500 	mov	w0, #0x28                  	// #40
  400c4c:	b9011fa0 	str	w0, [x29, #284]
  400c50:	a90e7fbf 	stp	xzr, xzr, [x29, #224]
  400c54:	a90f7fbf 	stp	xzr, xzr, [x29, #240]
  400c58:	f90083bf 	str	xzr, [x29, #256]
  400c5c:	52800140 	mov	w0, #0xa                   	// #10
  400c60:	b900e3a0 	str	w0, [x29, #224]
  400c64:	528001e0 	mov	w0, #0xf                   	// #15
  400c68:	b900e7a0 	str	w0, [x29, #228]
  400c6c:	52800280 	mov	w0, #0x14                  	// #20
  400c70:	b900eba0 	str	w0, [x29, #232]
  400c74:	52800320 	mov	w0, #0x19                  	// #25
  400c78:	b900efa0 	str	w0, [x29, #236]
  400c7c:	528003c0 	mov	w0, #0x1e                  	// #30
  400c80:	b900f3a0 	str	w0, [x29, #240]
  400c84:	52800500 	mov	w0, #0x28                  	// #40
  400c88:	b900f7a0 	str	w0, [x29, #244]
  400c8c:	a90bffbf 	stp	xzr, xzr, [x29, #184]
  400c90:	a90cffbf 	stp	xzr, xzr, [x29, #200]
  400c94:	f9006fbf 	str	xzr, [x29, #216]
  400c98:	52800140 	mov	w0, #0xa                   	// #10
  400c9c:	b900bba0 	str	w0, [x29, #184]
  400ca0:	528001e0 	mov	w0, #0xf                   	// #15
  400ca4:	b900bfa0 	str	w0, [x29, #188]
  400ca8:	52800280 	mov	w0, #0x14                  	// #20
  400cac:	b900c3a0 	str	w0, [x29, #192]
  400cb0:	52800320 	mov	w0, #0x19                  	// #25
  400cb4:	b900c7a0 	str	w0, [x29, #196]
  400cb8:	528003c0 	mov	w0, #0x1e                  	// #30
  400cbc:	b900cba0 	str	w0, [x29, #200]
  400cc0:	52800500 	mov	w0, #0x28                  	// #40
  400cc4:	b900cfa0 	str	w0, [x29, #204]
  400cc8:	a9097fbf 	stp	xzr, xzr, [x29, #144]
  400ccc:	a90a7fbf 	stp	xzr, xzr, [x29, #160]
  400cd0:	f9005bbf 	str	xzr, [x29, #176]
  400cd4:	52800140 	mov	w0, #0xa                   	// #10
  400cd8:	b90093a0 	str	w0, [x29, #144]
  400cdc:	528001e0 	mov	w0, #0xf                   	// #15
  400ce0:	b90097a0 	str	w0, [x29, #148]
  400ce4:	52800280 	mov	w0, #0x14                  	// #20
  400ce8:	b9009ba0 	str	w0, [x29, #152]
  400cec:	52800320 	mov	w0, #0x19                  	// #25
  400cf0:	b9009fa0 	str	w0, [x29, #156]
  400cf4:	528003c0 	mov	w0, #0x1e                  	// #30
  400cf8:	b900a3a0 	str	w0, [x29, #160]
  400cfc:	52800500 	mov	w0, #0x28                  	// #40
  400d00:	b900a7a0 	str	w0, [x29, #164]
  400d04:	a906ffbf 	stp	xzr, xzr, [x29, #104]
  400d08:	a907ffbf 	stp	xzr, xzr, [x29, #120]
  400d0c:	f90047bf 	str	xzr, [x29, #136]
  400d10:	52800140 	mov	w0, #0xa                   	// #10
  400d14:	b9006ba0 	str	w0, [x29, #104]
  400d18:	528001e0 	mov	w0, #0xf                   	// #15
  400d1c:	b9006fa0 	str	w0, [x29, #108]
  400d20:	52800280 	mov	w0, #0x14                  	// #20
  400d24:	b90073a0 	str	w0, [x29, #112]
  400d28:	52800320 	mov	w0, #0x19                  	// #25
  400d2c:	b90077a0 	str	w0, [x29, #116]
  400d30:	528003c0 	mov	w0, #0x1e                  	// #30
  400d34:	b9007ba0 	str	w0, [x29, #120]
  400d38:	52800500 	mov	w0, #0x28                  	// #40
  400d3c:	b9007fa0 	str	w0, [x29, #124]
  400d40:	a9047fbf 	stp	xzr, xzr, [x29, #64]
  400d44:	a9057fbf 	stp	xzr, xzr, [x29, #80]
  400d48:	f90033bf 	str	xzr, [x29, #96]
  400d4c:	52800140 	mov	w0, #0xa                   	// #10
  400d50:	b90043a0 	str	w0, [x29, #64]
  400d54:	528001e0 	mov	w0, #0xf                   	// #15
  400d58:	b90047a0 	str	w0, [x29, #68]
  400d5c:	52800280 	mov	w0, #0x14                  	// #20
  400d60:	b9004ba0 	str	w0, [x29, #72]
  400d64:	52800320 	mov	w0, #0x19                  	// #25
  400d68:	b9004fa0 	str	w0, [x29, #76]
  400d6c:	528003c0 	mov	w0, #0x1e                  	// #30
  400d70:	b90053a0 	str	w0, [x29, #80]
  400d74:	52800500 	mov	w0, #0x28                  	// #40
  400d78:	b90057a0 	str	w0, [x29, #84]
  400d7c:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  400d80:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  400d84:	f9001fbf 	str	xzr, [x29, #56]
  400d88:	52800140 	mov	w0, #0xa                   	// #10
  400d8c:	b9001ba0 	str	w0, [x29, #24]
  400d90:	528001e0 	mov	w0, #0xf                   	// #15
  400d94:	b9001fa0 	str	w0, [x29, #28]
  400d98:	52800280 	mov	w0, #0x14                  	// #20
  400d9c:	b90023a0 	str	w0, [x29, #32]
  400da0:	52800320 	mov	w0, #0x19                  	// #25
  400da4:	b90027a0 	str	w0, [x29, #36]
  400da8:	528003c0 	mov	w0, #0x1e                  	// #30
  400dac:	b9002ba0 	str	w0, [x29, #40]
  400db0:	52800500 	mov	w0, #0x28                  	// #40
  400db4:	b9002fa0 	str	w0, [x29, #44]
  400db8:	9104c3a0 	add	x0, x29, #0x130
  400dbc:	f900afa0 	str	x0, [x29, #344]
  400dc0:	f940afa0 	ldr	x0, [x29, #344]
  400dc4:	91001001 	add	x1, x0, #0x4
  400dc8:	f900afa1 	str	x1, [x29, #344]
  400dcc:	b9400001 	ldr	w1, [x0]
  400dd0:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400dd4:	91232000 	add	x0, x0, #0x8c8
  400dd8:	97fffdda 	bl	400540 <printf@plt>
  400ddc:	f940afa0 	ldr	x0, [x29, #344]
  400de0:	91001001 	add	x1, x0, #0x4
  400de4:	f900afa1 	str	x1, [x29, #344]
  400de8:	b9400001 	ldr	w1, [x0]
  400dec:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400df0:	91232000 	add	x0, x0, #0x8c8
  400df4:	97fffdd3 	bl	400540 <printf@plt>
  400df8:	f940afa0 	ldr	x0, [x29, #344]
  400dfc:	91001001 	add	x1, x0, #0x4
  400e00:	f900afa1 	str	x1, [x29, #344]
  400e04:	b9400001 	ldr	w1, [x0]
  400e08:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400e0c:	91232000 	add	x0, x0, #0x8c8
  400e10:	97fffdcc 	bl	400540 <printf@plt>
  400e14:	910423a0 	add	x0, x29, #0x108
  400e18:	f900afa0 	str	x0, [x29, #344]
  400e1c:	f940afa0 	ldr	x0, [x29, #344]
  400e20:	91001000 	add	x0, x0, #0x4
  400e24:	f900afa0 	str	x0, [x29, #344]
  400e28:	f940afa0 	ldr	x0, [x29, #344]
  400e2c:	b9400001 	ldr	w1, [x0]
  400e30:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400e34:	91236000 	add	x0, x0, #0x8d8
  400e38:	97fffdc2 	bl	400540 <printf@plt>
  400e3c:	f940afa0 	ldr	x0, [x29, #344]
  400e40:	91001000 	add	x0, x0, #0x4
  400e44:	f900afa0 	str	x0, [x29, #344]
  400e48:	f940afa0 	ldr	x0, [x29, #344]
  400e4c:	b9400001 	ldr	w1, [x0]
  400e50:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400e54:	91236000 	add	x0, x0, #0x8d8
  400e58:	97fffdba 	bl	400540 <printf@plt>
  400e5c:	f940afa0 	ldr	x0, [x29, #344]
  400e60:	91001000 	add	x0, x0, #0x4
  400e64:	f900afa0 	str	x0, [x29, #344]
  400e68:	f940afa0 	ldr	x0, [x29, #344]
  400e6c:	b9400001 	ldr	w1, [x0]
  400e70:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400e74:	91236000 	add	x0, x0, #0x8d8
  400e78:	97fffdb2 	bl	400540 <printf@plt>
  400e7c:	910383a0 	add	x0, x29, #0xe0
  400e80:	f900afa0 	str	x0, [x29, #344]
  400e84:	f940afa0 	ldr	x0, [x29, #344]
  400e88:	b9400000 	ldr	w0, [x0]
  400e8c:	11000402 	add	w2, w0, #0x1
  400e90:	f940afa1 	ldr	x1, [x29, #344]
  400e94:	b9000022 	str	w2, [x1]
  400e98:	b0000001 	adrp	x1, 401000 <ggg+0x438>
  400e9c:	9123a022 	add	x2, x1, #0x8e8
  400ea0:	2a0003e1 	mov	w1, w0
  400ea4:	aa0203e0 	mov	x0, x2
  400ea8:	97fffda6 	bl	400540 <printf@plt>
  400eac:	f940afa0 	ldr	x0, [x29, #344]
  400eb0:	b9400000 	ldr	w0, [x0]
  400eb4:	11000402 	add	w2, w0, #0x1
  400eb8:	f940afa1 	ldr	x1, [x29, #344]
  400ebc:	b9000022 	str	w2, [x1]
  400ec0:	b0000001 	adrp	x1, 401000 <ggg+0x438>
  400ec4:	9123a022 	add	x2, x1, #0x8e8
  400ec8:	2a0003e1 	mov	w1, w0
  400ecc:	aa0203e0 	mov	x0, x2
  400ed0:	97fffd9c 	bl	400540 <printf@plt>
  400ed4:	f940afa0 	ldr	x0, [x29, #344]
  400ed8:	b9400000 	ldr	w0, [x0]
  400edc:	11000402 	add	w2, w0, #0x1
  400ee0:	f940afa1 	ldr	x1, [x29, #344]
  400ee4:	b9000022 	str	w2, [x1]
  400ee8:	b0000001 	adrp	x1, 401000 <ggg+0x438>
  400eec:	9123a022 	add	x2, x1, #0x8e8
  400ef0:	2a0003e1 	mov	w1, w0
  400ef4:	aa0203e0 	mov	x0, x2
  400ef8:	97fffd92 	bl	400540 <printf@plt>
  400efc:	9102e3a0 	add	x0, x29, #0xb8
  400f00:	f900afa0 	str	x0, [x29, #344]
  400f04:	f940afa0 	ldr	x0, [x29, #344]
  400f08:	b9400000 	ldr	w0, [x0]
  400f0c:	11000401 	add	w1, w0, #0x1
  400f10:	f940afa0 	ldr	x0, [x29, #344]
  400f14:	b9000001 	str	w1, [x0]
  400f18:	f940afa0 	ldr	x0, [x29, #344]
  400f1c:	b9400001 	ldr	w1, [x0]
  400f20:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400f24:	9123e000 	add	x0, x0, #0x8f8
  400f28:	97fffd86 	bl	400540 <printf@plt>
  400f2c:	f940afa0 	ldr	x0, [x29, #344]
  400f30:	b9400000 	ldr	w0, [x0]
  400f34:	11000401 	add	w1, w0, #0x1
  400f38:	f940afa0 	ldr	x0, [x29, #344]
  400f3c:	b9000001 	str	w1, [x0]
  400f40:	f940afa0 	ldr	x0, [x29, #344]
  400f44:	b9400001 	ldr	w1, [x0]
  400f48:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400f4c:	9123e000 	add	x0, x0, #0x8f8
  400f50:	97fffd7c 	bl	400540 <printf@plt>
  400f54:	f940afa0 	ldr	x0, [x29, #344]
  400f58:	b9400000 	ldr	w0, [x0]
  400f5c:	11000401 	add	w1, w0, #0x1
  400f60:	f940afa0 	ldr	x0, [x29, #344]
  400f64:	b9000001 	str	w1, [x0]
  400f68:	f940afa0 	ldr	x0, [x29, #344]
  400f6c:	b9400001 	ldr	w1, [x0]
  400f70:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400f74:	9123e000 	add	x0, x0, #0x8f8
  400f78:	97fffd72 	bl	400540 <printf@plt>
  400f7c:	910243a0 	add	x0, x29, #0x90
  400f80:	f900afa0 	str	x0, [x29, #344]
  400f84:	f940afa0 	ldr	x0, [x29, #344]
  400f88:	b9400000 	ldr	w0, [x0]
  400f8c:	11000401 	add	w1, w0, #0x1
  400f90:	f940afa0 	ldr	x0, [x29, #344]
  400f94:	b9000001 	str	w1, [x0]
  400f98:	f940afa0 	ldr	x0, [x29, #344]
  400f9c:	b9400001 	ldr	w1, [x0]
  400fa0:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400fa4:	91242000 	add	x0, x0, #0x908
  400fa8:	97fffd66 	bl	400540 <printf@plt>
  400fac:	f940afa0 	ldr	x0, [x29, #344]
  400fb0:	b9400000 	ldr	w0, [x0]
  400fb4:	11000401 	add	w1, w0, #0x1
  400fb8:	f940afa0 	ldr	x0, [x29, #344]
  400fbc:	b9000001 	str	w1, [x0]
  400fc0:	f940afa0 	ldr	x0, [x29, #344]
  400fc4:	b9400001 	ldr	w1, [x0]
  400fc8:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400fcc:	91242000 	add	x0, x0, #0x908
  400fd0:	97fffd5c 	bl	400540 <printf@plt>
  400fd4:	f940afa0 	ldr	x0, [x29, #344]
  400fd8:	b9400000 	ldr	w0, [x0]
  400fdc:	11000401 	add	w1, w0, #0x1
  400fe0:	f940afa0 	ldr	x0, [x29, #344]
  400fe4:	b9000001 	str	w1, [x0]
  400fe8:	f940afa0 	ldr	x0, [x29, #344]
  400fec:	b9400001 	ldr	w1, [x0]
  400ff0:	b0000000 	adrp	x0, 401000 <ggg+0x438>
  400ff4:	91242000 	add	x0, x0, #0x908
  400ff8:	97fffd52 	bl	400540 <printf@plt>
  400ffc:	97fffe9a 	bl	400a64 <point>
  401000:	97fffed3 	bl	400b4c <modify_array>
  401004:	52800000 	mov	w0, #0x0                   	// #0
  401008:	a8d67bfd 	ldp	x29, x30, [sp], #352
  40100c:	d65f03c0 	ret

0000000000401010 <x>:
  401010:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401014:	910003fd 	mov	x29, sp
  401018:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  40101c:	52800180 	mov	w0, #0xc                   	// #12
  401020:	b9001ba0 	str	w0, [x29, #24]
  401024:	528001c0 	mov	w0, #0xe                   	// #14
  401028:	b9001fa0 	str	w0, [x29, #28]
  40102c:	52800200 	mov	w0, #0x10                  	// #16
  401030:	b90023a0 	str	w0, [x29, #32]
  401034:	910063a0 	add	x0, x29, #0x18
  401038:	f90017a0 	str	x0, [x29, #40]
  40103c:	f94017a0 	ldr	x0, [x29, #40]
  401040:	b9400001 	ldr	w1, [x0]
  401044:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401048:	91246000 	add	x0, x0, #0x918
  40104c:	97fffd3d 	bl	400540 <printf@plt>
  401050:	f94017a0 	ldr	x0, [x29, #40]
  401054:	91002000 	add	x0, x0, #0x8
  401058:	b9400001 	ldr	w1, [x0]
  40105c:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401060:	9124a000 	add	x0, x0, #0x928
  401064:	97fffd37 	bl	400540 <printf@plt>
  401068:	d503201f 	nop
  40106c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401070:	d65f03c0 	ret

0000000000401074 <y>:
  401074:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401078:	910003fd 	mov	x29, sp
  40107c:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  401080:	52800180 	mov	w0, #0xc                   	// #12
  401084:	b9001ba0 	str	w0, [x29, #24]
  401088:	528001c0 	mov	w0, #0xe                   	// #14
  40108c:	b90023a0 	str	w0, [x29, #32]
  401090:	52800200 	mov	w0, #0x10                  	// #16
  401094:	b90027a0 	str	w0, [x29, #36]
  401098:	910063a0 	add	x0, x29, #0x18
  40109c:	f90017a0 	str	x0, [x29, #40]
  4010a0:	f94017a0 	ldr	x0, [x29, #40]
  4010a4:	b9400001 	ldr	w1, [x0]
  4010a8:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4010ac:	91246000 	add	x0, x0, #0x918
  4010b0:	97fffd24 	bl	400540 <printf@plt>
  4010b4:	f94017a0 	ldr	x0, [x29, #40]
  4010b8:	91002000 	add	x0, x0, #0x8
  4010bc:	b9400001 	ldr	w1, [x0]
  4010c0:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4010c4:	9124a000 	add	x0, x0, #0x928
  4010c8:	97fffd1e 	bl	400540 <printf@plt>
  4010cc:	d503201f 	nop
  4010d0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4010d4:	d65f03c0 	ret

00000000004010d8 <w>:
  4010d8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4010dc:	910003fd 	mov	x29, sp
  4010e0:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  4010e4:	52800180 	mov	w0, #0xc                   	// #12
  4010e8:	b9001ba0 	str	w0, [x29, #24]
  4010ec:	528001c0 	mov	w0, #0xe                   	// #14
  4010f0:	b9001fa0 	str	w0, [x29, #28]
  4010f4:	52800200 	mov	w0, #0x10                  	// #16
  4010f8:	b90023a0 	str	w0, [x29, #32]
  4010fc:	910063a0 	add	x0, x29, #0x18
  401100:	f90017a0 	str	x0, [x29, #40]
  401104:	f94017a0 	ldr	x0, [x29, #40]
  401108:	b9400001 	ldr	w1, [x0]
  40110c:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401110:	9124e000 	add	x0, x0, #0x938
  401114:	97fffd0b 	bl	400540 <printf@plt>
  401118:	f94017a0 	ldr	x0, [x29, #40]
  40111c:	91002000 	add	x0, x0, #0x8
  401120:	b9400001 	ldr	w1, [x0]
  401124:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401128:	91252000 	add	x0, x0, #0x948
  40112c:	97fffd05 	bl	400540 <printf@plt>
  401130:	d503201f 	nop
  401134:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401138:	d65f03c0 	ret

000000000040113c <z>:
  40113c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401140:	910003fd 	mov	x29, sp
  401144:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  401148:	52800180 	mov	w0, #0xc                   	// #12
  40114c:	b9001ba0 	str	w0, [x29, #24]
  401150:	528001c0 	mov	w0, #0xe                   	// #14
  401154:	b90023a0 	str	w0, [x29, #32]
  401158:	52800200 	mov	w0, #0x10                  	// #16
  40115c:	b90027a0 	str	w0, [x29, #36]
  401160:	910063a0 	add	x0, x29, #0x18
  401164:	f90017a0 	str	x0, [x29, #40]
  401168:	f94017a0 	ldr	x0, [x29, #40]
  40116c:	b9400001 	ldr	w1, [x0]
  401170:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401174:	9124e000 	add	x0, x0, #0x938
  401178:	97fffcf2 	bl	400540 <printf@plt>
  40117c:	f94017a0 	ldr	x0, [x29, #40]
  401180:	91002000 	add	x0, x0, #0x8
  401184:	b9400001 	ldr	w1, [x0]
  401188:	90000000 	adrp	x0, 401000 <ggg+0x438>
  40118c:	91252000 	add	x0, x0, #0x948
  401190:	97fffcec 	bl	400540 <printf@plt>
  401194:	d503201f 	nop
  401198:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40119c:	d65f03c0 	ret

00000000004011a0 <hhh>:
  4011a0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4011a4:	910003fd 	mov	x29, sp
  4011a8:	97ffff9a 	bl	401010 <x>
  4011ac:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4011b0:	91256000 	add	x0, x0, #0x958
  4011b4:	97fffcdf 	bl	400530 <puts@plt>
  4011b8:	97ffffaf 	bl	401074 <y>
  4011bc:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4011c0:	91256000 	add	x0, x0, #0x958
  4011c4:	97fffcdb 	bl	400530 <puts@plt>
  4011c8:	97ffffc4 	bl	4010d8 <w>
  4011cc:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4011d0:	91256000 	add	x0, x0, #0x958
  4011d4:	97fffcd7 	bl	400530 <puts@plt>
  4011d8:	97ffffd9 	bl	40113c <z>
  4011dc:	d503201f 	nop
  4011e0:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4011e4:	d65f03c0 	ret

00000000004011e8 <v>:
  4011e8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4011ec:	910003fd 	mov	x29, sp
  4011f0:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4011f4:	91260000 	add	x0, x0, #0x980
  4011f8:	d2800503 	mov	x3, #0x28                  	// #40
  4011fc:	d2800102 	mov	x2, #0x8                   	// #8
  401200:	d2800021 	mov	x1, #0x1                   	// #1
  401204:	97fffccf 	bl	400540 <printf@plt>
  401208:	d503201f 	nop
  40120c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401210:	d65f03c0 	ret

0000000000401214 <array>:
  401214:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401218:	910003fd 	mov	x29, sp
  40121c:	910043a0 	add	x0, x29, #0x10
  401220:	90000001 	adrp	x1, 401000 <ggg+0x438>
  401224:	912a2021 	add	x1, x1, #0xa88
  401228:	4c40a020 	ld1	{v0.16b, v1.16b}, [x1]
  40122c:	4c00a000 	st1	{v0.16b, v1.16b}, [x0]
  401230:	910043a0 	add	x0, x29, #0x10
  401234:	91002000 	add	x0, x0, #0x8
  401238:	910043a4 	add	x4, x29, #0x10
  40123c:	90000001 	adrp	x1, 401000 <ggg+0x438>
  401240:	91268023 	add	x3, x1, #0x9a0
  401244:	aa0003e2 	mov	x2, x0
  401248:	aa0403e1 	mov	x1, x4
  40124c:	aa0303e0 	mov	x0, x3
  401250:	97fffcbc 	bl	400540 <printf@plt>
  401254:	910043a0 	add	x0, x29, #0x10
  401258:	91001000 	add	x0, x0, #0x4
  40125c:	910043a4 	add	x4, x29, #0x10
  401260:	90000001 	adrp	x1, 401000 <ggg+0x438>
  401264:	91270023 	add	x3, x1, #0x9c0
  401268:	aa0003e2 	mov	x2, x0
  40126c:	aa0403e1 	mov	x1, x4
  401270:	aa0303e0 	mov	x0, x3
  401274:	97fffcb3 	bl	400540 <printf@plt>
  401278:	910043a0 	add	x0, x29, #0x10
  40127c:	91001000 	add	x0, x0, #0x4
  401280:	910043a4 	add	x4, x29, #0x10
  401284:	90000001 	adrp	x1, 401000 <ggg+0x438>
  401288:	9127a023 	add	x3, x1, #0x9e8
  40128c:	aa0003e2 	mov	x2, x0
  401290:	aa0403e1 	mov	x1, x4
  401294:	aa0303e0 	mov	x0, x3
  401298:	97fffcaa 	bl	400540 <printf@plt>
  40129c:	910043a0 	add	x0, x29, #0x10
  4012a0:	b9400001 	ldr	w1, [x0]
  4012a4:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4012a8:	91284000 	add	x0, x0, #0xa10
  4012ac:	97fffca5 	bl	400540 <printf@plt>
  4012b0:	910043a0 	add	x0, x29, #0x10
  4012b4:	b9400001 	ldr	w1, [x0]
  4012b8:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4012bc:	9128a000 	add	x0, x0, #0xa28
  4012c0:	97fffca0 	bl	400540 <printf@plt>
  4012c4:	910043a0 	add	x0, x29, #0x10
  4012c8:	b9400001 	ldr	w1, [x0]
  4012cc:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4012d0:	91290000 	add	x0, x0, #0xa40
  4012d4:	97fffc9b 	bl	400540 <printf@plt>
  4012d8:	910043a0 	add	x0, x29, #0x10
  4012dc:	b9401401 	ldr	w1, [x0, #20]
  4012e0:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4012e4:	91294000 	add	x0, x0, #0xa50
  4012e8:	97fffc96 	bl	400540 <printf@plt>
  4012ec:	910043a0 	add	x0, x29, #0x10
  4012f0:	91005000 	add	x0, x0, #0x14
  4012f4:	b9400001 	ldr	w1, [x0]
  4012f8:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4012fc:	9129a000 	add	x0, x0, #0xa68
  401300:	97fffc90 	bl	400540 <printf@plt>
  401304:	52800000 	mov	w0, #0x0                   	// #0
  401308:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40130c:	d65f03c0 	ret

0000000000401310 <array_point>:
  401310:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401314:	910003fd 	mov	x29, sp
  401318:	910123a0 	add	x0, x29, #0x48
  40131c:	d100c000 	sub	x0, x0, #0x30
  401320:	90000001 	adrp	x1, 401000 <ggg+0x438>
  401324:	912a2021 	add	x1, x1, #0xa88
  401328:	4c40a020 	ld1	{v0.16b, v1.16b}, [x1]
  40132c:	4c00a000 	st1	{v0.16b, v1.16b}, [x0]
  401330:	910063a0 	add	x0, x29, #0x18
  401334:	f9001fa0 	str	x0, [x29, #56]
  401338:	f9401fa0 	ldr	x0, [x29, #56]
  40133c:	91002001 	add	x1, x0, #0x8
  401340:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401344:	912aa000 	add	x0, x0, #0xaa8
  401348:	aa0103e2 	mov	x2, x1
  40134c:	f9401fa1 	ldr	x1, [x29, #56]
  401350:	97fffc7c 	bl	400540 <printf@plt>
  401354:	f9401fa0 	ldr	x0, [x29, #56]
  401358:	91001001 	add	x1, x0, #0x4
  40135c:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401360:	912b0000 	add	x0, x0, #0xac0
  401364:	aa0103e2 	mov	x2, x1
  401368:	f9401fa1 	ldr	x1, [x29, #56]
  40136c:	97fffc75 	bl	400540 <printf@plt>
  401370:	f9401fa0 	ldr	x0, [x29, #56]
  401374:	91001001 	add	x1, x0, #0x4
  401378:	90000000 	adrp	x0, 401000 <ggg+0x438>
  40137c:	912b8000 	add	x0, x0, #0xae0
  401380:	aa0103e2 	mov	x2, x1
  401384:	f9401fa1 	ldr	x1, [x29, #56]
  401388:	97fffc6e 	bl	400540 <printf@plt>
  40138c:	f9401fa0 	ldr	x0, [x29, #56]
  401390:	b9400001 	ldr	w1, [x0]
  401394:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401398:	912c0000 	add	x0, x0, #0xb00
  40139c:	97fffc69 	bl	400540 <printf@plt>
  4013a0:	f9401fa0 	ldr	x0, [x29, #56]
  4013a4:	b9400001 	ldr	w1, [x0]
  4013a8:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4013ac:	912c4000 	add	x0, x0, #0xb10
  4013b0:	97fffc64 	bl	400540 <printf@plt>
  4013b4:	f9401fa0 	ldr	x0, [x29, #56]
  4013b8:	b9400001 	ldr	w1, [x0]
  4013bc:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4013c0:	912c8000 	add	x0, x0, #0xb20
  4013c4:	97fffc5f 	bl	400540 <printf@plt>
  4013c8:	f9401fa0 	ldr	x0, [x29, #56]
  4013cc:	91004000 	add	x0, x0, #0x10
  4013d0:	b9400401 	ldr	w1, [x0, #4]
  4013d4:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4013d8:	912cc000 	add	x0, x0, #0xb30
  4013dc:	97fffc59 	bl	400540 <printf@plt>
  4013e0:	f9401fa0 	ldr	x0, [x29, #56]
  4013e4:	91004000 	add	x0, x0, #0x10
  4013e8:	91001000 	add	x0, x0, #0x4
  4013ec:	b9400001 	ldr	w1, [x0]
  4013f0:	90000000 	adrp	x0, 401000 <ggg+0x438>
  4013f4:	912d0000 	add	x0, x0, #0xb40
  4013f8:	97fffc52 	bl	400540 <printf@plt>
  4013fc:	52800000 	mov	w0, #0x0                   	// #0
  401400:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401404:	d65f03c0 	ret

0000000000401408 <evaluate>:
  401408:	d10143ff 	sub	sp, sp, #0x50
  40140c:	910083e0 	add	x0, sp, #0x20
  401410:	f9001fe0 	str	x0, [sp, #56]
  401414:	910083e0 	add	x0, sp, #0x20
  401418:	f9001fe0 	str	x0, [sp, #56]
  40141c:	910083e0 	add	x0, sp, #0x20
  401420:	f9001fe0 	str	x0, [sp, #56]
  401424:	910083e0 	add	x0, sp, #0x20
  401428:	f90027e0 	str	x0, [sp, #72]
  40142c:	910023e0 	add	x0, sp, #0x8
  401430:	f90027e0 	str	x0, [sp, #72]
  401434:	9100e3e0 	add	x0, sp, #0x38
  401438:	f90023e0 	str	x0, [sp, #64]
  40143c:	f94023e0 	ldr	x0, [sp, #64]
  401440:	910083e1 	add	x1, sp, #0x20
  401444:	f9000001 	str	x1, [x0]
  401448:	f94023e0 	ldr	x0, [sp, #64]
  40144c:	910023e1 	add	x1, sp, #0x8
  401450:	f9000001 	str	x1, [x0]
  401454:	910023e0 	add	x0, sp, #0x8
  401458:	f90023e0 	str	x0, [sp, #64]
  40145c:	d503201f 	nop
  401460:	910143ff 	add	sp, sp, #0x50
  401464:	d65f03c0 	ret

0000000000401468 <tttt>:
  401468:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40146c:	910003fd 	mov	x29, sp
  401470:	97ffff69 	bl	401214 <array>
  401474:	97ffffa7 	bl	401310 <array_point>
  401478:	52800000 	mov	w0, #0x0                   	// #0
  40147c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401480:	d65f03c0 	ret

0000000000401484 <f>:
  401484:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401488:	910003fd 	mov	x29, sp
  40148c:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401490:	912d6000 	add	x0, x0, #0xb58
  401494:	97fffc27 	bl	400530 <puts@plt>
  401498:	52800020 	mov	w0, #0x1                   	// #1
  40149c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4014a0:	d65f03c0 	ret

00000000004014a4 <test_pf>:
  4014a4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4014a8:	910003fd 	mov	x29, sp
  4014ac:	b0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4014b0:	91010000 	add	x0, x0, #0x40
  4014b4:	90000001 	adrp	x1, 401000 <ggg+0x438>
  4014b8:	91121021 	add	x1, x1, #0x484
  4014bc:	f9000001 	str	x1, [x0]
  4014c0:	b0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4014c4:	91010000 	add	x0, x0, #0x40
  4014c8:	f9400000 	ldr	x0, [x0]
  4014cc:	d63f0000 	blr	x0
  4014d0:	b0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4014d4:	91010000 	add	x0, x0, #0x40
  4014d8:	90000001 	adrp	x1, 401000 <ggg+0x438>
  4014dc:	91121021 	add	x1, x1, #0x484
  4014e0:	f9000001 	str	x1, [x0]
  4014e4:	b0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  4014e8:	91010000 	add	x0, x0, #0x40
  4014ec:	f9400000 	ldr	x0, [x0]
  4014f0:	d63f0000 	blr	x0
  4014f4:	97ffffe4 	bl	401484 <f>
  4014f8:	d503201f 	nop
  4014fc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401500:	d65f03c0 	ret

0000000000401504 <t>:
  401504:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401508:	910003fd 	mov	x29, sp
  40150c:	90000000 	adrp	x0, 401000 <ggg+0x438>
  401510:	912dc000 	add	x0, x0, #0xb70
  401514:	97fffc07 	bl	400530 <puts@plt>
  401518:	d503201f 	nop
  40151c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401520:	d65f03c0 	ret

0000000000401524 <point_define>:
  401524:	d14007ff 	sub	sp, sp, #0x1, lsl #12
  401528:	a9007bfd 	stp	x29, x30, [sp]
  40152c:	910003fd 	mov	x29, sp
  401530:	d2800000 	mov	x0, #0x0                   	// #0
  401534:	d63f0000 	blr	x0
  401538:	d503201f 	nop
  40153c:	a9407bfd 	ldp	x29, x30, [sp]
  401540:	914007ff 	add	sp, sp, #0x1, lsl #12
  401544:	d65f03c0 	ret

0000000000401548 <iii>:
  401548:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40154c:	910003fd 	mov	x29, sp
  401550:	97ffffd5 	bl	4014a4 <test_pf>
  401554:	97ffffd4 	bl	4014a4 <test_pf>
  401558:	97ffffeb 	bl	401504 <t>
  40155c:	97ffffea 	bl	401504 <t>
  401560:	97ffffe9 	bl	401504 <t>
  401564:	97ffffe8 	bl	401504 <t>
  401568:	97ffffe7 	bl	401504 <t>
  40156c:	52800000 	mov	w0, #0x0                   	// #0
  401570:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401574:	d65f03c0 	ret

0000000000401578 <main>:
  401578:	52800000 	mov	w0, #0x0                   	// #0
  40157c:	d65f03c0 	ret

0000000000401580 <__libc_csu_init>:
  401580:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401584:	910003fd 	mov	x29, sp
  401588:	a901d7f4 	stp	x20, x21, [sp, #24]
  40158c:	90000094 	adrp	x20, 411000 <__FRAME_END__+0xf47c>
  401590:	90000095 	adrp	x21, 411000 <__FRAME_END__+0xf47c>
  401594:	91374294 	add	x20, x20, #0xdd0
  401598:	913722b5 	add	x21, x21, #0xdc8
  40159c:	a902dff6 	stp	x22, x23, [sp, #40]
  4015a0:	cb150294 	sub	x20, x20, x21
  4015a4:	f9001ff8 	str	x24, [sp, #56]
  4015a8:	2a0003f6 	mov	w22, w0
  4015ac:	aa0103f7 	mov	x23, x1
  4015b0:	9343fe94 	asr	x20, x20, #3
  4015b4:	aa0203f8 	mov	x24, x2
  4015b8:	97fffbc2 	bl	4004c0 <_init>
  4015bc:	b4000194 	cbz	x20, 4015ec <__libc_csu_init+0x6c>
  4015c0:	f9000bb3 	str	x19, [x29, #16]
  4015c4:	d2800013 	mov	x19, #0x0                   	// #0
  4015c8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  4015cc:	aa1803e2 	mov	x2, x24
  4015d0:	aa1703e1 	mov	x1, x23
  4015d4:	2a1603e0 	mov	w0, w22
  4015d8:	91000673 	add	x19, x19, #0x1
  4015dc:	d63f0060 	blr	x3
  4015e0:	eb13029f 	cmp	x20, x19
  4015e4:	54ffff21 	b.ne	4015c8 <__libc_csu_init+0x48>  // b.any
  4015e8:	f9400bb3 	ldr	x19, [x29, #16]
  4015ec:	a941d7f4 	ldp	x20, x21, [sp, #24]
  4015f0:	a942dff6 	ldp	x22, x23, [sp, #40]
  4015f4:	f9401ff8 	ldr	x24, [sp, #56]
  4015f8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4015fc:	d65f03c0 	ret

0000000000401600 <__libc_csu_fini>:
  401600:	d65f03c0 	ret

Disassembly of section .fini:

0000000000401604 <_fini>:
  401604:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401608:	910003fd 	mov	x29, sp
  40160c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401610:	d65f03c0 	ret
